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Take care when changing the interval timer time base. The
recommended procedure is as follows:
with FSEL[1:0] = 00 and 512 Hz with FSEL[1:0] = 01 in the
Interrupt Pins Configuration SFR (INTPR, 0xFF).
1.
2.
3.
If the Alarm Interval SFR (INTVAL, 0xA6) is going to
be modified, write to this register first. Then, wait for
one 128 Hz clock cycle to synchronize with the RTC,
64,000 cycles at a 4.096 MHz instruction cycle clock.
Disable the interval timer by clearing the ITEN bit in the
RTC Configuration SFR (TIMECON, 0xA1). Then, wait
for one 128 Hz clock cycle to synchronize with the RTC,
64,000 cycles at a 4.096 MHz instruction cycle clock.
Read the TIMECON SFR to ensure that the ITEN bit is
A shorter window of 0.244 sec is offered for fast calibration
during PSM0 or PSM1. Two output frequencies are offered for
this RTC calibration output mode: 500 Hz with FSEL[1:0] = 10
and 16.384 kHz with FSEL[1:0] = 11 in the INTPR SFR. Note
that for the 0.244 sec calibration window, the RTC is clocked
125 times faster than in normal mode, resulting in timekeeping
registers that represent seconds/125, minutes/125, and hours/125
instead of seconds, minutes, and hours. Therefore, this mode
should be used for calibration only.
4.
clear. If it is not, wait for another 128 Hz clock cycle.
Set the time base bits (ITS[1:0]) in the TIMECON SFR to
configure the interval. Wait for a 128 Hz clock cycle for this
change to take effect.
Table 119. RTC Calibration Options
Calibration
Option FSEL[1:0] Window (Sec)
Normal Mode 0 00 30.5
f RTCCAL (Hz)
1
The RTC alarm event wakes the 8052 MCU core if the MCU is
in PSM2 when the alarm event occurs.
RTC CALIBRATION
Normal Mode 1
Calibration Mode 0
Calibration Mode 1
01
10
11
30.5
0.244
0.244
512
500
16,384
The RTC provides registers to calibrate the nominal external
crystal frequency and its variation over temperature. A frequency
error up to ±248 ppm can be calibrated by the RTC circuitry,
which adds or subtracts pulses from the external crystal signal.
The nominal crystal frequency should be calibrated with the
RTC nominal compensation register so that the clock going into
the RTC is precisely 32.768 kHz at 25°C. The RTC Temperature
Compensation SFR (TEMPCAL, 0xF7) is used to compensate
for the external crystal drift over temperature by adding or
subtracting additional pulses based on temperature.
The LSB of each RTC compensation register represents a
±2 ppm frequency error. The RTC compensation circuitry adds
the RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
and the RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
to determine how much compensation is required. Note that
When no RTC compensation is applied, that is, when RTC
Nominal Compensation SFR (RTCCOMP, 0xF6) and RTC
Temperature Compensation SFR (TEMPCAL, 0xF7) are equal
to 0, the nominal compensation required to account for the
error in the external crystal can be determined. In this case, it is
not necessary to wait for an entire calibration window to determine
the error in the pulse output. Calculating the error in frequency
between two consecutive pulses on the P0.2/CF1/RTCCAL pin
is sufficient.
The value to write to the RTC Nominal Compensation SFR
(RTCCOMP, 0xF6) is calculated from the % error or seconds per
day error on the frequency output. Each LSB of the RTCCOMP
SFR represents 2 ppm of correction where 1 sec/day error is
equal to 11.57 ppm.
RTCCOMP = 5000 × (% Error )
the sum of these two registers is limited to ±248 ppm.
Calibration Flow
RTCCOMP =
1
2 × 11 . 57
× ( sec/day Error )
An RTC calibration pulse output is provided on the P0.2/CF1/
RTCCAL pin. Enable the RTC output by setting the RTCCAL
bit in the Interrupt Pins Configuration SFR (INTPR, 0xFF).
The RTC calibration is accurate to within ±2 ppm over a 30.5 sec
During calibration, user software writes the RTC with the
current time. Refer to the Read and Write Operations section
for more information on how to read and write the RTC
timekeeping registers.
window in all operational modes: PSM0, PSM1, and PSM2. Two
output frequencies are offered for the normal RTC mode: 1 Hz
Rev. 0 | Page 104 of 128
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